74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP

This page provides the datasheet information for the 74LS112A, a member of the 74LS112 DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP family.

Product Overview

Motorola

Part number	74LS112A
Manufacturer	Motorola
File Size	147.34 KB
Description	DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
Datasheet	74LS112A Datasheet
Additional preview pages of the 74LS112A datasheet.

individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH and the bistable will perform according to the truth table as long as minimum set-up and hold time are observed. Input data is transferred to the outputs on the negative-going edge of the clock pulse. SN54/74LS112A DUAL JK.

74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop (Fairchild Semiconductor)
74LS112 - Dual J-K Negative-edge-triggered Flip-Flops (Hitachi Semiconductor)
74LS11 - Triple 3-Input AND Gate (Fairchild Semiconductor)
74LS10 - TRIPLE 3-INPUT NAND GATE (ON Semiconductor)
74LS10 - Triple 3-Input NAND Gate (Fairchild Semiconductor)
74LS107 - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flops (ETC)
74LS109 - Dual J-K Flip-Flop (Agere Systems)
74LS109A - LOW POWER SCHOTTKY (ON Semiconductor)
74LS109A - Dual J-K Positive-Edge-Triggered Flip-Flops (Texas Instruments)
74LS12 - Dual Retriggerable Monostable Multivibrators (Hitachi Semiconductor)

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Published: Jan 7, 2017 |