DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54.
Motorola
74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs.
Fairchild Semiconductor
74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74.
National Semiconductor
DM74LS112A - NEGATIVE-EDGE-TRIGERED MASTER-SLAVE J-K FLIP-FLOPS
www.datasheet4u.com www.datasheet4u.com www.datasheet4u.com .
Fairchild Semiconductor
DM74LS112A - Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop
DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs August 1986 Revised March 2000 DM74.
Motorola
SN74LS112A - DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS112A dual JK flip-flop features individual J, K, clock, and asynchronous set and clear inputs.
Texas Instruments
SN74LS112A - Dual J-K Negative-Edge-Triggered Flip-Flops
PACKAGE OPTION ADDENDUM www.ti.com 24-Aug-2018 PACKAGING INFORMATION Orderable Device JM38510/07102BEA Status Package Type Package Pins Package .