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MC100E160 - 12-Bit Parity Generator/Checker

Features

  • an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y output LOW. 12-BIT PARITY.

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Datasheet preview – MC100E160

Datasheet Details

Part number MC100E160
Manufacturer Motorola
File Size 87.91 KB
Description 12-Bit Parity Generator/Checker
Datasheet download datasheet MC100E160 Datasheet
Additional preview pages of the MC100E160 datasheet.

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Full PDF Text Transcription

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www.DataSheet4U.com MOTOROLA SEMICONDUCTOR TECHNICAL DATA 12ĆBit Parity Generator/Checker MC10E160 MC100E160 The MC10E/100E160 is a 12-bit parity generator/checker. The Q output is HIGH when an odd number of inputs are HIGH. A HIGH on the Enable input (EN) forces the Q output LOW. The E160 also features an output register. Multiplexers direct the register input, giving the option of holding present data by asserting HOLD LOW, or of shifting data in through the S-IN pin by asserting SHIFT HIGH. The output register itself is clocked by a positive edge on CLK1 or CLK2 (or both). A HIGH on the reset pin (R) overrides to force the Y output LOW. 12-BIT PARITY GENERATOR/CHECKER • • • • • • • • Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 900ps Max.
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