Checker Datasheet | Specifications & PDF Download

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CD40101BMS December 1992 CMOS 9-Bit Parity Generator/Checker Features Pinout • High Voltage Type (20V Rating) • 100% Tested for Quiescent Current

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

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Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0

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• Inputs Are TTL-Voltage Compatible • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Flow-Through Architectu

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www.ti.com PACKAGE OPTION ADDENDUM 20-Feb-2024 PACKAGING INFORMATION Orderable Device SN54180J SNJ54180J SNJ54180J SNJ54180W SNJ54180W Status Pack

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HD74HC280 9-bit Odd/Even Parity Generator/Checker Description This parity generator/checker features odd/even outputs to facilitate operation of eith

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HCC/HCF40101B 9-BIT PARITY GENERATOR/CHECKER . . . . . . STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC

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ACTS280MS January 1996 Radiation Hardened 9-Bit Odd/ Even Parity Generator Checker Pinouts 14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2

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ACS280MS January 1996 Radiation Hardened 9-Bit Odd/ Even Parity Generator Checker Pinouts 14 PIN CERAMIC DUAL-IN-LINE MIL-STD-1835 DESIGNATOR, CDIP2-

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DM74AS286 9-Bit Parity Generator/Checker with Bus-Driver Parity I/O Port October 1986 Revised April 2000 DM74AS286 9-Bit Parity Generator/Checker wi

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC06 74HC/HCT/HCU/HCMOS Logic Family Specifications • The IC06

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www.DataSheet4U.com 74F401 CRC Generator/Checker April 1988 Revised August 1999 74F401 CRC Generator/Checker General Description The 74F401 Cycle R

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www.DataSheet4U.com 74F402 Serial Data Polynomial Generator/Checker April 1988 Revised August 1999 74F402 Serial Data Polynomial Generator/Checker

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HD74HC180 8-bit Odd/Even Parity Generator/Checker Description This universal, monolithic, 9-bit (8 data bits plus 1 parity bit) parity generator/chec

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• Inputs Are TTL-Voltage Compatible • Generates Either Odd or Even Parity for Nine Data Lines • Cascadable for n-Bits Parity • Flow-Through Architectu

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Unit: mm 19.20 20.32 Max 14 8 6.30 7.40 Max 1 2.39 Max 1.30 7 7.62 0.51 Min 2.54 Min 5.06 Max 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° + 0

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HCC/HCF40101B 9-BIT PARITY GENERATOR/CHECKER . . . . . . STANDARDIZED SYMMETRICAL OUTPUT CHARACTERISTICS QUIESCENT CURRENT SPECIFIED AT 20V FOR HCC

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