PIN D0 * D11 S-IN EN HOLD SHIFT CLK1, CLK2 R Q, Q Y, Y VCC, VCCO VEE NC FUNCTION ECL Data Inputs ECL Serial Data Input ECL Enable, active LOW ECL Hold, active LOW ECL Shift, active HIGH ECL Clock Inputs ECL Reset Inputs ECL Direct Output ECL Register Output Positive Supply Negative Supply No
www.DataSheet4U.com MC10E160, MC100E160 5V ECL 12-Bit Parity Generator/Checker The MC10E/100E160 is a 12-bit parity generator/checker.
The Q output is HIGH when an odd number of inputs are HIGH.
A HIGH on the Enable input (EN) forces the Q output LOW.
The 100 Series contains temperature compensation.
http://onsemi.com MARKING DIAGRAMS 1 28 Provides Odd-HIGH Parity of 12 Inputs Shiftable Output Register with Hold 9
MC100E160 Features
* Note AND8020
* Termination of ECL Logic Devices.) Resource Reference of Application Notes AN1404 AN1405 AN1406 AN1503 AN1504 AN1568 AN1596 AN1650 AN1672 AND8001 AND8002 AND8020
Datasheet Details
MC100E160
217.84 KB
12-bit parity generator/checker.
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