a 24mA TTL ouput stage with AC performance specified into a 50pF load capacitance. A 2:1 input mux is provided on chip to allow for distributing both system and diagnostic clock signals or designing clock redundancy into a system. With the SEL input held LOW the DO input will be selected, while the D1 input is selected when the SEL input is forced HIGH. MC10H645
1:9 TTL CLOCK.
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