MPC9600
Overview
- Multiplication of input frequency by 2, 3, 4 and 6
- Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable
- Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz
- Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz
- LVCMOS outputs
- Outputs disable to high impedance (except QFB)
- LVCMOS or LVPECL reference clock options
- 48 lead QFP packaging
- ±50 ps cycle-to-cycle jitter
- 150 ps maximum output-to-output skew
