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Motorola Electronic Components Datasheet

MTB75N06HD Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB75N06HD/D
Designer's Data Sheet
HDTMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This advanced
high–cell density HDTMOS power FET is designed to withstand
high energy in the avalanche and commutation modes. This new
energy efficient design also offers a drain–to–source diode with a
fast recovery time. Designed for low voltage, high speed switching
applications in power supplies, converters and PWM motor
controls, these devices are particularly well suited for bridge circuits
D
where diode speed and commutating safe operating areas are
critical and offer additional safety margin against unexpected
voltage transients.
Avalanche Energy Specified
G
Source–to–Drain Diode Recovery Time Comparable to a
Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured — Not Sheared
Specially Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
S
MTB75N06HD
Motorola Preferred Device
TMOS POWER FET
75 AMPERES
60 VOLTS
RDS(on) = 10 mOHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
VDSS 60 Vdc
Drain–to–Gate Voltage (RGS = 1.0 M)
VDGR 60 Vdc
Gate–to–Source Voltage — Continuous
Gate–to–Source Voltage — Non–Repetitive (tp 10 ms)
VGS
VGSM
± 20
± 30
Vdc
Vpk
Drain Current — Continuous
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp 10 µs)
ID 75 Adc
ID 50
IDM 225 Apk
Total Power Dissipation
Derate above 25°C
Total Power Dissipation @ TC = 25°C (1)
PD 125 Watts
1.0 W/°C
2.5 Watts
Operating and Storage Temperature Range
– 55 to 150
°C
Single Pulse Drain–to–Source Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 75 Apk, L = 0.177 mH, RG = 25 )
EAS 500 mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
RθJA
1.0 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from case for 10 seconds
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
TL 260 °C
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
E–FET, Designer’s and HDTMOS are trademarks of Motorola, Inc.
TMOS is a registered trademark of Motorola, Inc. Thermal Clad is a trademark of the Bergquist Company.
Preferred devices are Motorola recommended choices for future use and best overall value.
REV 1
©MMoottoororolal,aInTc.M19O9S5 Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB75N06HD Datasheet

TMOS POWER FET

No Preview Available !

MTB75N06HD
ELECTRICAL CHARACTERISTICS (TJ = 25°C unless otherwise noted)
Characteristic
Symbol
OFF CHARACTERISTICS
Drain–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
(Cpk 2.0) (3) V(BR)DSS
Zero Gate Voltage Drain Current
(VDS = 60 Vdc, VGS = 0 Vdc)
(VDS = 60 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current (VGS = ± 20 Vdc, VDS = 0 V)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Temperature Coefficient (Negative)
IDSS
IGSS
(Cpk 5.0) (3) VGS(th)
Static Drain–Source On–Resistance
(VGS = 10 Vdc, ID = 37.5 Adc)
(Cpk 2.0) (3)
Drain–Source On–Voltage (VGS = 10 Vdc)
(ID = 75 Adc)
(ID = 37.5 Adc, TJ = 125°C)
Forward Transconductance (VDS = 15 Vdc, ID = 37.5 Adc)
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(VDS = 30 Vdc, ID = 75 Adc,
VGS = 10 Vdc,
RG = 9.1 )
(VDS = 48 Vdc, ID = 75 Adc,
VGS = 10 Vdc)
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 75 Adc, VGS = 0 Vdc)
(IS = 75 Adc, VGS = 0 Vdc, TJ = 125°C)
RDS(on)
VDS(on)
gFS
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
VSD
Reverse Recovery Time
(IS = 75 Adc,
dIS/dt = 100 A/µs)
Reverse Recovery Stored Charge
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from contact screw on tab to center of die)
(Measured from the drain lead 0.25from package to center of die)
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
(1) Pulse Test: Pulse Width 300 µs, Duty Cycle 2%.
(2) Switching characteristics are independent of operating junction temperature.
(3) Reflects typical values.
Max limit – Typ
Cpk = 3 x SIGMA
trr
ta
tb
QRR
LD
LS
Min
60
2.0
15
Typ Max Unit
Vdc
68 —
60.4 — mV/°C
µAdc
— 10
— 100
5.0 100 nAdc
Vdc
3.0 4.0
8.38 — mV/°C
m
8.3 10
Vdc
0.7 0.9
0.53 0.8
32 — mhos
2800
928
180
3920
1300
252
pF
18 26
218 306
67 94
125 175
71 100
16.3 —
31 —
29.4 —
ns
nC
0.97
0.88
56
44
12
0.103
1.1
Vdc
ns
µC
nH
3.5 —
7.5 — nH
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB75N06HD
Description TMOS POWER FET
Maker Motorola
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MTB75N06HD Datasheet PDF






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