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Motorola Electronic Components Datasheet

MTB8N50E Datasheet

TMOS POWER FET

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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Order this document
by MTB8N50E/D
Designer's Data Sheet
TMOS E-FET.
High Energy Power FET
D2PAK for Surface Mount
N–Channel Enhancement–Mode Silicon Gate
The D2PAK package has the capability of housing a larger die
than any existing surface mount package which allows it to be used
in applications that require the use of surface mount components
with higher power and lower RDS(on) capabilities. This high voltage
MOSFET uses an advanced termination scheme to provide
enhanced voltage–blocking capability without degrading perfor-
mance over time. In addition, this advanced TMOS E–FET is
designed to withstand high energy in the avalanche and commuta-
tion modes. This new energy efficient design also offers a
drain–to–source diode with a fast recovery time. Designed for low
voltage, high speed switching applications in power supplies,
converters, PWM motor controls, these devices are particularly well
suited for bridge circuits where diode speed and commutating safe
operating areas are critical and offer additional safety margin
against unexpected voltage transients.
G
D
Robust High Voltage Termination
Avalanche Energy Specified
Source–to–Drain Diode Recovery Time Comparable
to a Discrete Fast Recovery Diode
Diode is Characterized for Use in Bridge Circuits
IDSS and VDS(on) Specified at Elevated Temperature
Short Heatsink Tab Manufactured – Not Sheared
Specifically Designed Leadframe for Maximum Power Dissipation
Available in 24 mm 13–inch/800 Unit Tape & Reel, Add T4 Suffix to Part Number
®
S
MTB8N50E
TMOS POWER FET
8.0 AMPERES
500 VOLTS
RDS(on) = 0.8 OHM
CASE 418B–02, Style 2
D2PAK
MAXIMUM RATINGS (TJ = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
Drain–to–Source Voltage
WDrain–to–Gate Voltage (RGS = 1.0 M )
Gate–to–Source Voltage – Continuous
Gate–to–Source Voltage – Non–repetitive (tp 10 ms)
VDSS
VDGR
VGS
VGSM
500 Vdc
500 Vdc
±20 Vdc
±40 Vpk
Drain Current — Continuous @ TC = 25°C
mDrain Current — Continuous @ TC = 100°C
Drain Current — Single Pulse (tp 10 s)
ID 8.0 Adc
ID 5.0
IDM 32 Apk
Total Power Dissipation @ TC = 25°C
Derate above 25°C
PD 125 Watts
1.0 W/°C
Operating and Storage Temperature Range
Single Pulse Drain–to–Source Avalanche Energy – STARTING TJ = 25°C
W(VDD = 25 Vdc, VGS = 10 Vdc, PEAK IL = 8.0 Apk, L = 16 mH, RG = 25 )
TJ, Tstg
EAS
– 55 to 150
510
°C
mJ
Thermal Resistance
– Junction–to–Case
– Junction–to–Ambient
– Junction–to–Ambient (1)
RqJC
RqJA
RqJA
1.0 °C/W
62.5
50
Maximum Lead Temperature for Soldering Purposes, 1/8from Case for 5 sec.
TL
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
This document contains information on a new product. Specifications and information herein are subject to change without notice.
E–FET and Designer’s are trademarks of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
260
°C
REV 1
© MMoototororloa,laIncT.M19O96S Power MOSFET Transistor Device Data
1


Motorola Electronic Components Datasheet

MTB8N50E Datasheet

TMOS POWER FET

No Preview Available !

MTB8N50E
ELECTRICAL CHARACTERISTICS (TC = 25°C unless otherwise noted)
Characteristic
Symbol Min Typ Max Unit
OFF CHARACTERISTICS
Drain–to–Source Breakdown Voltage
(VGS = 0 Vdc, ID = 250 µAdc)
Temperature Coefficient (Positive)
Zero Gate Voltage Drain Current
(VDS = 500 Vdc, VGS = 0 Vdc)
(VDS = 400 Vdc, VGS = 0 Vdc, TJ = 125°C)
Gate–Body Leakage Current
(VGS = ±20 Vdc, VDS = 0 Vdc)
ON CHARACTERISTICS (1)
Gate Threshold Voltage
(VDS = VGS, ID = 250 µAdc)
Threshold Temperature Coefficient (Negative)
V(BR)DSS
500
500
— Vdc
— mV/°C
IDSS
mAdc
— — 10
— — 100
IGSS
nAdc
— — 100
VGS(th)
2.0 3.0 4.0 Vdc
— 6.3 — mV/°C
Static Drain–to–Source On–Resistance
(VGS = 10 Vdc, ID = 4.0 Adc)
RDS(on)
Ohms
— 0.6 0.8
Drain–to–Source On–Voltage (VGS = 10 Vdc)
(ID = 8.0 Adc)
(ID = 4.0 Adc, TJ = 125°C)
VDS(on)
Vdc
— — 7.2
— — 6.4
Forward Transconductance
(VDS = 15 Vdc, ID = 4.0 Adc)
gFS mhos
4.0 —
DYNAMIC CHARACTERISTICS
Input Capacitance
Output Capacitance
Transfer Capacitance
SWITCHING CHARACTERISTICS (2)
Turn–On Delay Time
Rise Time
Turn–Off Delay Time
Fall Time
Gate Charge
(see Figure 8)
(VDS = 25 Vdc, VGS = 0 Vdc,
f = 1.0 MHz)
W(RGon = 9.1 )
(VDS = 400 Vdc, ID = 8.0 Adc,
VGS = 10 Vdc)
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
QT
Q1
Q2
Q3
1450
1680
pF
— 190 264
— 45.4 144
— 15 50 ns
— 33 72
— 40 150
— 32 60
— 40 64 nC
— 8.0 —
— 17 —
— 17.3 —
SOURCE–DRAIN DIODE CHARACTERISTICS
Forward On–Voltage
(IS = 8.0 Adc, VGS = 0 Vdc)
(IS = 8.0 Adc, VGS = 0 Vdc, TJ = 125°C)
Reverse Recovery Time
Reverse Recovery Stored Charge
m(IS = 8.0 Adc, VGS = 0 Vdc,
dIS/dt = 100 A/ s)
VSD
trr
ta
tb
QRR
Vdc
— 1.2 2.0
— 1.1 —
— 320 —
ns
— 179 —
— 141 —
— 3.0 — mC
INTERNAL PACKAGE INDUCTANCE
Internal Drain Inductance
(Measured from the drain lead 0.25from package to center of die)
LD nH
— 4.5 —
Internal Source Inductance
(Measured from the source lead 0.25from package to source bond pad)
m(1) Pulse Test: Pulse Width 300 s, Duty Cycle 2.0%.
(2) Switching characteristics are independent of operating junction temperature.
LS
— 7.5 —
2 Motorola TMOS Power MOSFET Transistor Device Data


Part Number MTB8N50E
Description TMOS POWER FET
Maker Motorola
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