UPD16633B
Key Features
- Capable of outputting 64 values by means of 5-by-2 external power modules (10 units) and a D/A converter
- Output dynamic range 9.8 VP-P min. (@VDD2 = 10.0 V)
- CMOS level input
- Input of 6 bits (gradation data) by 6 dots
- High-speed data transfer: fmax. = 45 MHz (internal data transfer speed when operating at 3.0 V)
- Apply for only dot inversion
- Display data inversion function (POL2 terminal.)
- Single bank arrangement is possible (loaded with slim TCP)
