Datasheet4U Logo Datasheet4U.com

UPD44164085 - (UPD44164085/185/365) 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION

Description

technology using full CMOS six-transistor memory cell.

Features

  • 1.8 ± 0.1 V power supply and HSTL I/O.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Separate independent read and write data ports.
  • DDR read or write operation initiated each cycle.
  • Pipelined double data rate operation.
  • Separate data input/output bus.
  • Two-tick burst for low DDR transaction size.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two outpu.

📥 Download Datasheet

Datasheet Details

Part number UPD44164085
Manufacturer NEC
File Size 375.36 KB
Description (UPD44164085/185/365) 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION
Datasheet download datasheet UPD44164085 Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
uPD44325092B 36M-BIT QDR II SRAM Renesas
uPD44325182B 36M-BIT QDR II SRAM Renesas
uPD44325362B 36M-BIT QDR II SRAM Renesas
UPD449 2048 x 8-Bit Static CMOS RAM NEC Electronics
UPD4066B Quad Analog Switch / Miltiplexer ETC

Other Datasheets by NEC

Part Number Description
UPD44164082 (UPD44164082/182/362) 18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164084 (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION
UPD44164182 (UPD44164082/182/362) 18M-BIT DDRII SRAM 2-WORD BURST OPERATION
UPD44164184 (UPD44164084/184/364) 18M-BIT DDRII SRAM 4-WORD BURST OPERATION
UPD44164185 (UPD44164085/185/365) 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION

Full PDF Text Transcription

Click to expand full text
DATA SHEET MOS INTEGRATED CIRCUIT µPD44164085, 44164185, 44164365 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION Description The µPD44164085 is a 2,097,152-word by 8-bit, the µPD44164185 is a 1,048,576-word by 18-bit and the µPD44164365 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44164085, µPD44164185 and µPD44164365 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration.
Published: |