UPD44164085 Datasheet | NEC

DATA SHEET MOS INTEGRATED CIRCUIT µPD44164085, 44164185, 44164365 18M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION Description The µPD44164085 is a 2,097,152-word by 8-bit, the µPD44164185 is a 1,048,576-word by 18-bit and the µPD44164365 is a 524,288-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44164085, µPD44164185 and µPD44164365 integrates unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K. These products are suitable for application which require synchronous operation, high speed, low voltage, high density and wide bit configuration. These products are packaged in 165-pin PLASTIC BGA. Features - 1.8 ± 0.1 V power supply and HSTL I/O - DLL circuitry for wide output data valid window and future frequency scaling - Separate independent read and write data ports - DDR read or write operation initiated each cycle - Pipelined double data rate operation - Separate data input/output bus - Two-tick burst for low DDR transaction size - Two input clocks (K and /K) for precise DDR timing at clock rising edges only - Two output clocks (C and /C) for precise flight time and clock skew matching-clock and data delivered together to receiving device - Internally self-timed write control - Clock-stop capability with µs restart - User programmable impedance output - Fast clock cycle time : 4.0 ns (250 MHz), 5.0 ns (200 MHz), 6.0 ns (167 MHz) - Simple control logic for easy depth expansion - JTAG boundary scan The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest...