2-WORD Datasheet | Specifications & PDF Download

'97.4.7 MITSUBISHI LSIs M5M5256DP,KP,FP,VP,RV -45LL-W,-55LL-W,-70LL-W, -45XL-W,-55XL-W,-70XL-W 262144-BIT (32768-WORD BY 8-BIT) CMOS STATIC RAM DES

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2001.May Rev.0.1 MITSUBISHI LSIs Advanced Information Notice: This is not final specification. Some parametric limits are subject to change. M5M5Y5

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MICROCIRCUIT CORPORATION DESCRIPTION The Accutek AK591024 high density memory modules is a random access memory organized in 1 Meg x 9 bit words. The

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MICROCIRCUIT CORPORATION DESCRIPTION The Accutek AK5322048BW high density memory module is a CMOS dynamic RAM organized in 2048K x 32 bit words. The m

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GM71C17800C GM71CS17800CL 2,097,152 WORDS x 8 BIT CMOS DYNAMIC RAM Description The GM71C(S)17800C/CL is the new generation dynamic RAM organized 2,09

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CY7C1423KV18/CY7C1424KV18 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture 36-Mbit DDR II SIO SRAM Two-Word Burst Architecture Features ■ 36-Mbit

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HM628512B Series 4 M SRAM (512-kword × 8-bit) ADE-203-903D (Z) Rev. 3.0 Aug. 24, 1999 Description The Hitachi HM628512B is a 4-Mbit static RAM organi

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HM62W8511HC Series 4M High Speed SRAM (512-kword × 8-bit) ADE-203-1201 (Z) Preliminary Rev. 0.0 Sep. 20, 2000 Description The HM62W8511HC is a 4-Mbit

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CY62157H MoBL® 8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting Code (ECC) 8-Mbit (512K words × 16-bit) Static RAM with Error-Correcting

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72-Mbit QDR® II+ SRAM Four-Word Burst Architecture with RadStop™ Technology Radiation Performance Radiation Data ■ Total Dose =300 Krad ■ Soft error

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CY7C2163KV18/CY7C2165KV18 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) with ODT 18-Mbit QDR® II+ SRAM Four-Word Burst

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CY7C1248KV18/CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture

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CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

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CY7C1668KV18 CY7C1670KV18 144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.5 Cycle Read Latency) 144-Mbit DDR II+ SRAM Two-Word Burst Architectur

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CXK5T81000ATN/AYN -10LLX/12LLX 131072-word × 8-bit High Speed CMOS Static RAM Description The CXK5T81000ATN/AYN is a high speed CMOS static RAM organi

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CXK5T8512TM/TN -10LLX/12LLX 65536-word × 8-bit High Speed CMOS Static RAM Description The CXK5T8512TM/TN is a high speed CMOS static RAM organized as

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CXK5V16100TM -85LLX/10LLX 65536-word × 16-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. Descri

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CXK5V8257BTM/BYM/BM -70LL/10LL 32768-word × 8-bit High Speed CMOS Static RAM For the availability of this product, please contact the sales office. De

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PRELIMINARY DATA SHEET 1GB Unbuffered DDR SDRAM DIMM EBD11ED8ABFB (128M words × 72 bits, 2 Banks) Description The EBD11ED8ABFB is 128M words × 72 bit

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