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CY7C1248KV18

36-Mbit DDR II+ SRAM Two-Word Burst Architecture

CY7C1248KV18 Features

* 36-Mbit density (2M × 18, 1M × 36)

* 450 MHz clock for high bandwidth

* Two-word burst for reducing address bus frequency

* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz

* Available in 2.0 clock cycle latency

* Two input clocks (K and K) for pre

CY7C1248KV18 Datasheet (1.17 MB)

Preview of CY7C1248KV18 PDF

Datasheet Details

Part number:

CY7C1248KV18

Manufacturer:

Cypress Semiconductor

File Size:

1.17 MB

Description:

36-mbit ddr ii+ sram two-word burst architecture.
CY7C1248KV18/CY7C1250KV18 36-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 36-Mbit DDR II+ SRAM Two-Word Burst Architecture .

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TAGS

CY7C1248KV18 36-Mbit DDR II + SRAM Two-Word Burst Architecture Cypress Semiconductor

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