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CY7C1548KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture

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Description

CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture .

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Datasheet Specifications

Part number
CY7C1548KV18
Manufacturer
Cypress Semiconductor
File Size
631.46 KB
Datasheet
CY7C1548KV18-CypressSemiconductor.pdf
Description
72-Mbit DDR II+ SRAM Two-Word Burst Architecture

Features

* 72-Mbit density (4M × 18, 2M × 36)
* 450-MHz clock for high bandwidth
* 2-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
* Available in 2.0 clock cycle latency
* Two input clocks (K and K) for preci

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