* 72-Mbit density (4M × 18, 2M × 36)
* 450-MHz clock for high bandwidth
* 2-word burst for reducing address bus frequency
* Double data rate (DDR) interfaces (data transferred at 900 MHz) at 450 MHz
* Available in 2.0 clock cycle latency
* Two input clocks (K and K) for preci
CY7C1548KV18 Datasheet (631.46 KB)
CY7C1548KV18
Cypress Semiconductor
631.46 KB
72-mbit ddr ii+ sram two-word burst architecture.
CY7C1548KV18/CY7C1550KV18 72-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency) 72-Mbit DDR II+ SRAM Two-Word Burst Architecture .
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