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UPD44324085 - 36M-BIT DDRII SRAM

Description

The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a 2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

Features

  • 1.8 ± 0.1 V power supply and HSTL I/O.
  • DLL circuitry for wide output data valid window and future frequency scaling.
  • Separate independent read and write data ports.
  • DDR read or write operation initiated each cycle.
  • Pipelined double data rate operation.
  • Separate data input/output bus.
  • Two-tick burst for low DDR transaction size.
  • Two input clocks (K and /K) for precise DDR timing at clock rising edges only.
  • Two outpu.

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Datasheet Details

Part number UPD44324085
Manufacturer NEC
File Size 375.99 KB
Description 36M-BIT DDRII SRAM
Datasheet download datasheet UPD44324085 Datasheet

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Other Datasheets by NEC

Part Number Description
UPD44324082 36M-BIT DDRII SRAM
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UPD44324094 36M-BIT DDRII SRAM
UPD44324095 36M-BIT DDRII SRAM

Full PDF Text Transcription

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www.DataSheet4U.com PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD44324085, 44324095, 44324185, 44324365 36M-BIT DDRII SRAM SEPARATE I/O 2-WORD BURST OPERATION Description The µPD44324085 is a 4,194,304-word by 8-bit, the µPD44324095 is a 4,194,304-word by 9-bit, the µPD44324185 is a 2,097,152-word by 18-bit and the µPD44324365 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44324085, µPD44324095, µPD44324185 and µPD44324365 integrate unique synchronous peripheral circuitry and a burst counter. All input registers controlled by an input clock pair (K and /K) are latched on the positive edge of K and /K.
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