UPD44324182
Description
The µPD44324082 is a 4,194,304-word by 8-bit, the µPD44324092 is a 4,194,304-word by 9-bit, the µPD44324182 is a 2,097,152-word by 18-bit and the µPD44324362 is a 1,048,576-word by 36-bit synchronous double data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell.
Key Features
- 1.8 ± 0.1 V power supply
- 165-pin PLASTIC BGA package (13 x 15)
- HSTL Interface
- DLL circuitry for wide output data valid window and future frequency scaling
- Pipelined double data rate operation
- Two-tick burst for low DDR transaction size
- Two input clocks (K and K#) for precise DDR timing at clock rising edges only
- Two output clocks (C and C#) for precise flight time and clock skew matching-clock and data delivered together to receiving device
- Internally self-timed write control
- Clock-stop capability. Normal operation is restored in 1,024 cycles after clock is resumed
