128m-bit synchronous dram 4-bank/ lvttl.
* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge
* Pulsed interface
* Possible to assert random column address in every c.
The µPD45128441, 45128841, 45128163 are high-speed 134,217,728-bit synchronous dynamic random-access memories, organized as 8,388,608 × 4 × 4, 4,194,304 × 8 × 4, 2,097,152 × 16 × 4 (word × bit × bank), respectively. The synchronous DRAMs achieved hig.
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