UPD4516161D Datasheet - Elpida

UPD4516161D 16M Bit Synchronous DRAM

The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words × 16 bits × 2 banks respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge .

UPD4516161D Features

* Fully Synchronous Dynamic RAM, with all signals referenced to a positive clock edge

* Pulsed interface

* Possible to assert random column address in every cycle

* Dual internal banks controlled by A11

* Byte control by LDQM and UDQM

* Programmable Wr

UPD4516161D_Elpida.pdf