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S7I321884M Datasheet 1mx36 & 2mx18 Ddrii Cio Bl4 Sram

Manufacturer: NETSOL

Overview: SS77I3I32233668844MM SS77I3I32211888844MM 11MMxx3366 && 22MMxx1188 DDDDRRIIII CCIIOO BBLL44 SSRRAAMM 36Mb DDRII CIO BL4 SRAM Specification 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. For updates or additional information about Netsol products, please contact to netsol@netsol.co.kr Rev. 1.2 May 2013 -1- S7I323684M S7I321884M 1Mx36 & 2Mx18 DDRII CIO BL4 SRAM Document Title 1Mx36 & 2Mx18 - Bit DDRII CIO Burst Length of 4 SRAM Revision History Rev. No. History 0.0 Initial Draft 1.0 Final spec release Add current spec value 1.1 Change Thermal Resistance JA value from 20.8C/W to 16.3C/W 1.2 Change DLL locking time spec to 1024cycles from 2048cycles Draft Date Mar. 2012 Feb. 2013 Remark Preliminary Final Apr. 2013 Final May 2013 Final Rev. 1.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Registered address, control and data in.

S7I321884M Distributor

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