Description
The S7I323684M and S7I321884M are 37,748,736-bits DDR Common I/O Synchronous Pipelined Burst SRAMs.
They are organized as 1,048,576 words by 36bits for S7I323684M and 2,097,152 words by 18 bits for S7I321884M.
Features
- 1.8V+0.1V/-0.1V Power Supply.
- DLL circuitry for wide output data valid window and future fre-
quency scaling.
- I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
- Pipelined, double-data rate operation.
- Common data input/output bus.
- HSTL I/O.
- Full data coherency, providing most current data.
- Synchronous pipeline read with self timed late write.
- Registered address, control and data in.