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S7K6418U2M Datasheet 2mx36 & 4mx18 Ddrii+ Cio Bl2 Sram

Manufacturer: NETSOL

Overview: SSSS7777KKKK6666444413318668UUUU2222MMMM 22MMxx3366 && 44MMxx1188 DDDDRRIIII++ CCIIOO BBLL22 SSRRAAMM 72Mb DDRII+ CIO BL2 SRAM Specification (2.5 Clock Read Latency) 165FBGA with Pb & Pb Free (ROHS Compliant) NETSOL RESERVES THE RIGHT TO CHANGE PRODUCTS, INFORMATION AND SPECIFICATIONS WITHOUT NOTICE. Products and specifications discussed herein are for reference purposes only. All information discussed herein is provided on an "AS IS" basis, without warranties of any kind. This document and all information discussed herein remain the sole and exclusive property of NETSOL. No license of any patent, copyright, mask work, trademark or any other intellectual property right is granted by one party to the other party under this document, by implication, estoppel or otherwise. For updates or additional information about Netsol products, please contact to netsol@netsol.co.kr Rev. 1.0 Jun. 2014 -1- S7K6436U2M S7K6418U2M 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM Document Title 2Mx36 & 4Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM (2.5 Clock Read Latency) Revision History Rev. No. History 1.0 Final spec release Draft Date Jun. 2014 Remark Final Rev. 1.0 Jun. 2014 -2- S7K6436U2M S7K6418U2M 2Mx36 & 4Mx18 DDRII+ CIO BL2 SRAM 2Mx36 & 4Mx18 - Bit DDRII+ CIO Burst Length of 2 SRAM (2.

This datasheet includes multiple variants, all published together in a single manufacturer document.

Key Features

  • Key Parameters.
  • 1.8V+0.1V/-0.1V Power Supply.
  • DLL circuitry for wide output data valid window and future fre- quency scaling.
  • I/O Supply Voltage 1.5V+0.1V/-0.1V for 1.5V I/O, 1.8V+0.1V/-0.1V for 1.8V I/O.
  • Pipelined, double-data rate operation.
  • Common data input/output bus.
  • HSTL I/O.
  • Full data coherency, providing most current data.
  • Synchronous pipeline read with self timed late write.
  • Read latency : 2.5 clo.

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