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74ABT843 - 9-bit interface latch

General Description

The 74ABT843 Bus interface latch is designed to eliminate the extra packages required to buffer existing registers and provide extra data width for wider data/address paths of buses carrying parity.

Key Features

  • High speed parallel latches.
  • Extra data width for wide address/data paths or buses carrying parity.
  • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors.
  • Slim DIP 300 mil package.
  • Broadside pinout.
  • Output capability: +64mA/.
  • 32mA.
  • Latch-up protection exceeds 500mA per Jedec Std 17.
  • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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INTEGRATED CIRCUITS 74ABT843 9-bit interface latch with set and reset (3-State) Product specification Supersedes data of 1995 Sep 06 IC23 Data Handbook 1998 Jan 16 Philips Semiconductors Philips Semiconductors 9-bit bus interface latch with set and reset (3-State) Product specification 74ABT843 FEATURES • High speed parallel latches • Extra data width for wide address/data paths or buses carrying parity • Ideal where high speed, light loading, or increased fan-in are required with MOS microprocessors • Slim DIP 300 mil package • Broadside pinout • Output capability: +64mA/–32mA • Latch-up protection exceeds 500mA per Jedec Std 17 • ESD protection exceeds 2000V per MIL STD 883 Method 3015 and 200V per Machine Model • Power-up 3-State • Power-up reset DESCRIPTION The 74ABT843 Bus int