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74ABTH16841A - 20-bit bus interface latch

This page provides the datasheet information for the 74ABTH16841A, a member of the 74ABTH 20-bit bus interface latch family.

Description

The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity.

The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs.

The flip-flops appear transparent to the data when Latch Enable (nLE) is High.

Features

  • High speed parallel latches.
  • Live insertion/extraction permitted.
  • Extra data width for wide address/data paths or buses carrying.
  • Power-up 3-State.
  • 74ABTH16841A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs parity.

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Datasheet Details

Part number 74ABTH16841A
Manufacturer NXP
File Size 100.22 KB
Description 20-bit bus interface latch
Datasheet download datasheet 74ABTH16841A Datasheet
Additional preview pages of the 74ABTH16841A datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS www.DataSheet4U.net 74ABT16841A 74ABTH16841A 20-bit bus interface latch (3-State) Product specification Supersedes data of 1995 Sep 28 IC23 Data Handbook 1998 Feb 27 Philips Semiconductors Philips Semiconductors Product specification 20-bit bus interface latch (3-State) 74ABT16841A 74ABTH16841A FEATURES • High speed parallel latches • Live insertion/extraction permitted • Extra data width for wide address/data paths or buses carrying • Power-up 3-State • 74ABTH16841A incorporates bus-hold data inputs which eliminate the need for external pull-up resistors to hold unused inputs parity DESCRIPTION The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity.
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