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74AHC138 Datasheet

3-to-8 line decoder/demultiplexer; inverting

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INTEGRATED CIRCUITS
DATA SHEET
74AHC138; 74AHCT138
3-to-8 line decoder/demultiplexer;
inverting
Product specification
Supersedes data of 1999 Mar 31
File under Integrated Circuits, IC06
1999 Sep 27


NXP Semiconductors Electronic Components Datasheet

74AHC138 Datasheet

3-to-8 line decoder/demultiplexer; inverting

No Preview Available !

Philips Semiconductors
3-to-8 line decoder/demultiplexer; inverting
Product specification
74AHC138;
74AHCT138
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Multiple input enable for easy
expansion
Ideal for memory chip select
decoding
Inputs accept voltages higher than
VCC
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT138 decoders accept three binary weighted address inputs
(A0, A1 and A2) and when enabled, provide 8 mutually exclusive active LOW
outputs (Y0 to Y7).
The ‘138’ features three enable inputs: two active LOW (E1 and E2) and one
active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3
is HIGH.
This multiple enable function allows easy parallel expansion of the ‘138’ to a
1-of-32 (5 to 32 lines) decoder with just four ‘138’ ICs and one inverter.
The ‘138’ can be used as an eight output demultiplexer by using one of the
active LOW enable inputs as the data input and the remaining enable inputs as
strobes. Unused enable inputs must be permanently tied to their appropriate
active HIGH or LOW state.
The ‘138’ is identical to the ‘238’ but has inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
CI
CO
CPD
propagation delay An to Yn
propagation delay E3 to Yn; En to Yn
input capacitance
output capacitance
power dissipation capacitance
CL = 15 pF; VCC = 5 V
CL = 15 pF; VCC = 5 V
VI = VCC or GND
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
TYPICAL
AHC
4.4
4.2
3.0
4.0
18
AHCT
4.4
4.3
3.0
4.0
23
UNIT
ns
ns
pF
pF
pF
1999 Sep 27
2


Part Number 74AHC138
Description 3-to-8 line decoder/demultiplexer; inverting
Maker NXP
Total Page 16 Pages
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