74AHC138 - 3-to-8 line decoder/demultiplexer

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NXP

74AHC138 3-to-8 line decoder/demultiplexer by NXP - Datasheet Preview — Datasheet preview – 74AHC138

Datasheet Details

Part number	74AHC138
Manufacturer	NXP
File Size	84.13 KB
Description	3-to-8 line decoder/demultiplexer
Datasheet	74AHC138 Datasheet
Additional preview pages of the 74AHC138 datasheet.

Product details

Description

74AHC138; 74AHCT138 The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with low power Schottky TTL (LSTTL).They are specified in compliance with JEDEC standard No.7A.The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0, A1 and A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7).The ‘138’

Features

ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V CDM EIA/JESD22-C101 exceeds 1000 V.
Balanced propagation delays.
All inputs have Schmitt-trigger actions.
Multiple input enable for easy expansion.
Ideal for memory chip select decoding.
Inputs accept voltages higher than VCC.
For AHC only: operates with CMOS input levels.
For AHCT only: operates with TTL input levels.
Specified.

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Published: Apr 3, 2005 |