74AHC138 Description
74AHCT138 The 74AHC/AHCT138 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard No. The 74AHC/AHCT138 decoders accept three binary weighted address inputs (A0, A1 and A2) and when enabled, provide 8 mutually exclusive active LOW outputs (Y0 to Y7).
74AHC138 Key Features
- Balanced propagation delays
- All inputs have Schmitt-trigger actions
- Multiple input enable for easy expansion
- Ideal for memory chip select decoding
- Inputs accept voltages higher than VCC
- For AHC only: operates with CMOS input levels
- For AHCT only: operates with TTL input levels
- Specified from -40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. DESCRIPTION