74AHC139D Datasheet | Nexperia

74AHC139; 74AHCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 02 - 9 May 2008 Product data sheet 1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin patible with Low-power Schottky TTL (LSTTL). It is specified in pliance with JEDEC standard No. 7-A. The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable input can be used as the data input for...