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74AHC139 - Dual 2-to-4 line decoder/demultiplexer

General Description

The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL).

It is specified in compliance with JEDEC standard No.

7-A.

Key Features

  • I Balanced propagation delays I All inputs have Schmitt-trigger actions I Inputs accept voltages higher than VCC I Input levels: N For 74AHC139: CMOS level N For 74AHCT139: TTL level I ESD protection: N HBM EIA/JESD22-A114E exceeds 2000 V N MM EIA/JESD22-A115-A exceeds 200 V N CDM EIA/JESD22-C101C exceeds 1000 V I Multiple package options I Specified from.
  • 40 °C to +85 °C and from.
  • 40 °C to +125 °C 3. Ordering information Table 1. Ordering information Type number Package Tempera.

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Datasheet Details

Part number 74AHC139
Manufacturer Nexperia
File Size 574.96 KB
Description Dual 2-to-4 line decoder/demultiplexer
Datasheet download datasheet 74AHC139 Datasheet

Full PDF Text Transcription for 74AHC139 (Reference)

Note: Below is a high-fidelity text extraction (approx. 800 characters) for 74AHC139. For precise diagrams, and layout, please refer to the original PDF.

74AHC139; 74AHCT139 Dual 2-to-4 line decoder/demultiplexer Rev. 02 — 9 May 2008 Product data sheet 1. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate ...

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. General description The 74AHC139; 74AHCT139 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with JEDEC standard No. 7-A. The 74AHC139; 74AHCT139 is a high-speed, dual 2-to-4 line decoder/demultiplexer. This device has two independent decoders, each accepting two binary weighted inputs (nA0 and nA1) and providing four mutually exclusive active LOW outputs (nY0 to nY3). Each decoder has an active LOW enable input (nE). When nE is HIGH, every output is forced HIGH. The enable input can be used as the data input for a 1-to-4 demultiplexer application

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