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74AHC138D - 3-to-8 line decoder/demultiplexer

This page provides the datasheet information for the 74AHC138D, a member of the 74AHC138 3-to-8 line decoder/demultiplexer family.

Description

The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL).

They are specified in compliance with JEDEC standard No.

7A.

Features

  • Balanced propagation delays.
  • All inputs have Schmitt-trigger action.
  • Demultiplexing capability.
  • Multiple input enable for easy expansion.
  • Ideal for memory chip select decoding.
  • Inputs accepts voltages higher than VCC.
  • For 74AHC138 only: operates with CMOS input levels.
  • For 74AHCT138 only: operates with TTL input levels.
  • ESD protection:.
  • HBM JESD22-A114E exceeds 2000 V.
  • MM JESD22-A115-A exceeds 200.

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Datasheet preview – 74AHC138D

Datasheet Details

Part number 74AHC138D
Manufacturer nexperia
File Size 256.07 KB
Description 3-to-8 line decoder/demultiplexer
Datasheet download datasheet 74AHC138D Datasheet
Additional preview pages of the 74AHC138D datasheet.

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Full PDF Text Transcription

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74AHC138; 74AHCT138 3-to-8 line decoder/demultiplexer; inverting Rev. 5 — 10 September 2020 Product data sheet 1. General description The 74AHC138; 74AHCT138 are high-speed Si-gate CMOS devices and are pin compatible with Low power Schottky TTL (LSTTL). They are specified in compliance with JEDEC standard No. 7A. The 74AHC138; 74AHCT138 is a 3-to-8 line decoder/demultiplexer. It accepts three binary weighted address inputs (A0, A1 and A2) and, when enabled, provides eight mutually exclusive outputs (Y0 to Y7) that are LOW when selected. There are three enable inputs: two active LOW (E1 and E2) and one active HIGH (E3). Every output will be HIGH unless E1 and E2 are LOW and E3 is HIGH.
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