900,000+ datasheet pdf search and download

Datasheet4U offers most rated semiconductors data sheet pdf




NXP Semiconductors Electronic Components Datasheet

74AHC374 Datasheet

Octal D-type flip-flop; positive edge-trigger; 3-state

No Preview Available !

INTEGRATED CIRCUITS
DATA SHEET
74AHC374; 74AHCT374
Octal D-type flip-flop; positive
edge-trigger; 3-state
Product specification
Supersedes data of 1998 Dec 11
File under Integrated Circuits, IC06
1999 Sep 28


NXP Semiconductors Electronic Components Datasheet

74AHC374 Datasheet

Octal D-type flip-flop; positive edge-trigger; 3-state

No Preview Available !

Philips Semiconductors
Octal D-type flip-flop; positive edge-trigger; 3-state
Product specification
74AHC374;
74AHCT374
FEATURES
ESD protection:
HBM EIA/JESD22-A114-A
exceeds 2000 V
MM EIA/JESD22-A115-A
exceeds 200 V
CDM EIA/JESD22-C101
exceeds 1000 V
Balanced propagation delays
All inputs have Schmitt-trigger
actions
Inputs accepts voltages higher than
VCC
Common 3-state output enable
input
ICC category: MSI
For AHC only:
operates with CMOS input levels
For AHCT only:
operates with TTL input levels
Specified from
40 to +85 and +125 °C.
DESCRIPTION
The 74AHC/AHCT374 are high-speed Si-gate CMOS devices and are pin
compatible with low power Schottky TTL (LSTTL). They are specified in
compliance with JEDEC standard No. 7A.
The 74AHC/AHCT374 are octal D-type flip-flops featuring separate D-type
inputs for each flip-flop and 3-state outputs for bus oriented applications.
A clock (CP) and an output enable (OE) input are common to all flip-flops.
The 8 flip-flops will store the state of their individual D-inputs that meet the
set-up and hold times requirements on the LOW-to-HIGH CP transition.
When OE is LOW the contents of the 8 flip-flops are available at the outputs.
When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation
of the OE input does not affect the state of the flip-flops.
The ‘374’ is functionally identical to the ‘534’, but has non-inverting outputs.
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf 3.0 ns.
SYMBOL
PARAMETER
CONDITIONS
tPHL/tPLH
fmax
CI
CO
CPD
propagation delay;
CP to Qn
maximum clock frequency
input capacitance
output capacitance
power dissipation
capacitance
CL = 15 pF; VCC = 5 V
CL = 15 pF; VCC = 5 V
VI = VCC or GND
CL = 50 pF; f = 1 MHz;
notes 1 and 2
Notes
1. CPD is used to determine the dynamic power dissipation (PD in µW).
PD = CPD × VCC2 × fi + (CL × VCC2 × fo) where:
fi = input frequency in MHz;
fo = output frequency in MHz;
(CL × VCC2 × fo) = sum of outputs;
CL = output load capacitance in pF;
VCC = supply voltage in Volts.
2. The condition is VI = GND to VCC.
TYPICAL
AHC
3.5
AHCT
5.0
UNIT
ns
50
MHz
3.0 3.0 pF
4.0 4.0 pF
10 12 pF
1999 Sep 28
2


Part Number 74AHC374
Description Octal D-type flip-flop; positive edge-trigger; 3-state
Maker NXP
Total Page 20 Pages
PDF Download

74AHC374 Datasheet PDF

View PDF for Mobile








Similar Datasheet

1 74AHC373 Octal D-type transparant latch
nexperia
2 74AHC373 Octal D-type transparent latch; 3-state
NXP
3 74AHC374 Octal D-type flip-flop
nexperia
4 74AHC374 Octal D-type flip-flop; positive edge-trigger; 3-state
NXP
5 74AHC374-Q100 Octal D-type flip-flop
nexperia
6 74AHC377 Octal D-type flip-flop
nexperia
7 74AHC377-Q100 Octal D-type flip-flop
nexperia





Part Number Start With

0    1    2    3    4    5    6    7    8    9    A    B    C    D    E    F    G    H    I    J    K    L    M    N    O    P    Q    R    S    T    U    V    W    X    Y    Z

Site map

Webmaste! click here

Contact us

Buy Components

Privacy Policy