74AHC574 Datasheet | NXP Semiconductors

INTEGRATED CIRCUITS DATA SHEET 74AHC574; 74AHCT574 Octal D-type flip-flop; positive edge-trigger; 3-state Product specification File under Integrated Circuits, IC06 1999 Jun 16 Philips Semiconductors Product specification Octal D-type flip-flop; positive edge-trigger; 3-state Features - 3-state non-inverting outputs for bus oriented applications - 8-bit positive, edge-triggered register - ESD protection: HBM EIA/JESD22-A114-A exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V - Independent register and 3-state buffer operation - mon 3-state output enable input - Output capability; bus driver - ICC category: MSI - For AHC only: operates with CMOS input levels - For AHCT only: operates with TTL input levels - Specified from - 40 to +85 and +125 °C. QUICK REFERENCE DATA GND = 0 V; Tamb = 25 °C; tr = tf ≤ 3.0 ns. DESCRIPTION 74AHC574; 74AHCT574 The 74AHC/AHCT574 are high-speed Si-gate CMOS devices and are pin patible with low power Schottky TTL (LSTTL). They are specified in pliance with JEDEC standard no. 7A. The 74AHC/AHCT574 are octal D-type flip-flops featuring separate D-type inputs for each flip-flop and 3-state outputs for bus oriented applications. A clock (CP) and an output enable (OE) input are mon to all flip-flops. The 8 flip-flops will store the state of their individual D-inputs that meet the set-up and hold times requirements on the LOW-to-HIGH CP transition. When OE is LOW the contents of the 8 flip-flops are available at the outputs. When OE is HIGH, the outputs go to the high-impedance OFF-state. Operation of the OE input does not affect the state of the flip-flops. The ‘574’ is functionally identical to the ‘564’, but has non-inverting outputs. The ‘574’ is functionally identical to the ‘374’, but has a different pinning. TYPICAL SYMBOL t PHL/t PLH fmax CI CO CPD Notes 1. CPD is used to determine the dynamic power dissipation (PD in µW). PD = CPD × VCC2 × fi + ∑ (CL × VCC2 × fo) where: fi = input frequency in MHz; fo = output frequency...