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74F11 Datasheet Triple 3-input NAND gate

Manufacturer: NXP Semiconductors

General Description

COMMERCIAL RANGE VCC = 5V ±10%, Tamb = 0°C to +70°C N74F10N, N74F11N N74F10D, N74F11D PKG DWG # SOT27-1 SOT108-1 INPUT AND OUTPUT LOADING AND FAN OUT TABLE PINS Dna, Dnb, Dnc Qn Qn Data inputs Data output (74F10) Data output (74F11) DESCRIPTION 74F (U.L.) HIGH/LOW 1.0/1.0 50/33 50/33 LOAD VALUE HIGH/LOW 20µA/0.6mA 1.0mA/20mA 1.0mA/20mA NOTE: One (1.0) FAST unit load is defined as: 20µA in the High state and 0.6mA in the Low state.

PIN CONFIGURATIONS 74F10 D0a D0b D1a D1b D1c Q1 GND 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC D0c Q0 D2c D2b D2a Q2 D0a D0b D1a D1b D1c Q1 GND 1 2 3 4 5 6 7 74F11 14 13 12 11 10 9 8 VCC D0c Q0 D2c D2b D2a Q2 SF00055 SF00056 LOGIC SYMBOLS 74F10 1 2 13 3 4 5 9 10 11 1 2 13 74F11 3 4 5 9 10 11 D0a D0b D0c D1a D1b D1c D2a D2b D2c D0a D0b D0c D1a D1b D1c D2a D2b D2c Q0 Q1 Q2 Q0 Q1 Q2 VCC = Pin 14 GND = Pin 7 12 6 8 VCC = Pin 14 GND = Pin 7 12 6 8 SF00057 SF00058 September 20, 1989 2 853–0329 97683 Philips Semiconductors Product specification Gates 74F10, 74F11 IEC/IEEE SYMBOLS 74F10 1 2 13 3 4 5 9 10 11 8 6 74F11 1 12 2 13 3 4 5 9 10 11 8 6 & & 12 SF00059 SF00060 LOGIC DIAGRAMS 74F10 1 D0a 2 D0b 13 D0c D1a D1b D1c D2a D2b VCC = Pin 14 GND = Pin 7 D2c 3 4 5 9 10 11 VCC = Pin 14 GND = Pin 7 8 Q2 6 Q1 D0c D1a D1b D1c D2a D2b D2c 3 4 5 9 10 11 8 Q2 6 Q1 12 Q0 D0b 13 D0a 2 12 Q0 1 74F11 SF00061 SF00062 FUNCTION TABLE INPUTS Dna L L L L H H H Dnb L L H H L L H Dnc L H L H L H L OUTPUTS 74F10 Qn H H H H H H H L 74F11 Qn L L L L L L L H H H H NOTES: 1.

Overview

INTEGRATED CIRCUITS 74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate Product specification IC15 Data Handbook 1989 Sep 20 Philips Semiconductors Philips Semiconductors Product specification Gates 74F10 Triple 3-input NAND gate 74F11 Triple 3-input AND gate TYPE 74F10 74F11 TYPICAL PROPAGATION DELAY 3.5ns 4.2ns TYPICAL SUPPLY CURRENT (TOTAL) 3.3mA 5.