74F175A Overview
The 74F175A is a quad, edge-triggered D-type flip-flop with individual D inputs and both Q and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the Low-to-High clock transition is transferred to the corresponding flip-flop’s Q output. All Q outputs will be forced Low independently of clock or data inputs by a Low voltage level on the MR input. The device is useful for
74F175A Key Features
- Four edge-triggered D-type flip-flops
- Buffered mon clock
- Buffered asynchronous Master Reset
- True and plementary outputs
- Industrial temperature range available (-40°C to +85°C)
- PNP light loading inputs
