Datasheet4U Logo Datasheet4U.com

74HC595 - 8-bit serial-in serial or parallel-out shift register

Description

The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs.

Both the shift and storage register have separate clocks.

Features

  • Wide supply voltage range from 2.0 V to 6.0 V.
  • CMOS low power dissipation.
  • High noise immunity.
  • 8-bit serial input.
  • 8-bit serial or parallel output.
  • Storage register with 3-state outputs.
  • Shift register with direct clear.
  • 100 MHz (typical) shift out frequency.
  • Latch-up performance exceeds 100 mA per JESD 78 Class II Level B.
  • Complies with JEDEC standards:.
  • JESD8C (2.7 V to 3.6 V).
  • JESD7A.

📥 Download Datasheet

📁 Similar Datasheet

Part Number Description Manufacturer
74HC595 8-Bit Serial-In/Serial-Out or Parallel-Out Shift Register SG Micro
74HC595 8-Bit Serial-Input/Serial or Parallel-Output Shift Register ON Semiconductor
74HC595 8-bit Shift Register/Latch Hitachi
74HC595 8-bit shift register ST Microelectronics
74HC595 8-BIT SHIFT REGISTER Diodes

Other Datasheets by NXP Semiconductors

Part Number Description
74HC541 Octal buffer/line driver
74HC573 Octal D-type transparent latch
74HC574 Octal D-type flip-flop
74HC00 Quad 2-input NAND gate
74HC05 Hex inverter

Full PDF Text Transcription

Click to expand full text
74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Rev. 12 — 20 March 2024 Product data sheet 1. General description The 74HC595; 74HCT595 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and 3-state outputs. Both the shift and storage register have separate clocks. The device features a serial input (DS) and a serial output (Q7S) to enable cascading and an asynchronous reset MR input. A LOW on MR will reset the shift register. Data is shifted on the LOW-to-HIGH transitions of the SHCP input. The data in the shift register is transferred to the storage register on a LOW-to-HIGH transition of the STCP input.
Published: |