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HEF4022B Datasheet 4-stage divide-by-8 Johnson counter

Manufacturer: NXP Semiconductors

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General Description

The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).

The counter is advanced by either a LOW to HIGH transition at CP0 while CP1 is LOW or a HIGH to LOW transition at CP1 while CP0 is HIGH (see also function table).

Either CP0 or CP1 may be used as clock input to the HEF4022B MSI counter and the other clock input may be used as a clock enable input.

Overview

INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC.

Key Features

  • of the HEF4022B are:.
  • High speed.
  • Spike-free decoded outputs.
  • Carry output for cascading HEF4022B MSI Figure 7 shows a technique for extending the number of decoded output states for the HEF4022B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). Fig.7 Counter expansion. January 1995 8.

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