HEF4022B Datasheet PDF - NXP 4-stage divide-by-8 Johnson counter Specs

HEF4022B - 4-stage divide-by-8 Johnson counter

Datasheet Summary

Description

The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).

Features

of the HEF4022B are:.
High speed.
Spike-free decoded outputs.
Carry output for cascading HEF4022B MSI Figure 7 shows a technique for extending the number of decoded output states for the HEF4022B. Decoded outputs are sequential within each stage and from stage to stage, with no dead time (except propagation delay). Fig.7 Counter expansion. January 1995 8.

Datasheet Details

Part number	HEF4022B
Manufacturer	NXP
File Size	91.70 KB
Description	4-stage divide-by-8 Johnson counter
Datasheet	HEF4022B Datasheet
Additional preview pages of the HEF4022B datasheet.

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Full PDF Text Transcription

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INTEGRATED CIRCUITS DATA SHEET For a complete data sheet, please also download: • The IC04 LOCMOS HE4000B Logic Family Specifications HEF, HEC • The IC04 LOCMOS HE4000B Logic Package Outlines/Information HEF, HEC HEF4022B MSI 4-stage divide-by-8 Johnson counter Product speciﬁcation File under Integrated Circuits, IC04 January 1995 Philips Semiconductors Product speciﬁcation 4-stage divide-by-8 Johnson counter DESCRIPTION The HEF4022B is a 4-stage divide-by-8 Johnson counter with eight spike-free decoded active HIGH outputs (O0 to O7), an active LOW output from the most significant flip-flop (O4-7), active HIGH and active LOW clock inputs (CP0, CP1) and an overriding asynchronous master reset input (MR).

Published: Mar 23, 2005 |