* Built-in bias resistors R1 and R2 (typ. 10 kΩ each)
* Simplification of circuit design
* Reduces number of components and board space. APPLICATIONS
* Es.

* Especially suitable for space reduction in interface and driver circuits
* Inverter circuit configurations wit.

PNP resistor-equipped transistor in an SC-75 plastic package. NPN complement: PDTC114EE. PINNING PIN 1 2 3 DESCRIPTION base/input emitter/ground (+) collector/output MGA893 - 1 PDTA114EE handbook, halfpage 3 R1 1 R2 3 1 Top view 2 MAM345 2 Fi.

PDTA114E

PDTA114EEF

PDTA114EK

PDTA114EM

PDTA114EMB

PDTA114EQA

PDTA114ES

PDTA114ET

PDTA114EU

PDTA114

PDTA114T

PDTA114TE

PDTA114TK