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NXP Semiconductors Electronic Components Datasheet

S32R372 Datasheet

32-bit CPU

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NXP Semiconductors
Data Sheet: Technical Data
S32R372 Data Sheet
Features
• Dual issue computation cores: Power Architecture®
e200z7 32-bit CPU
• 1.3 MB on-chip code flash memory (FMC flash
memory) with ECC
• 1 MB on-chip SRAM with ECC
• RADAR processing
– Signal Processing Toolbox (SPT) for RADAR signal
processing acceleration
– Cross Triggering Engine (CTE) for precise timing
generation and triggering
– MIPICSI2 interface to connect external RADAR RX
ADCs
• Memory protection
– Each core memory protection unit provides 24
entries
– Data and instruction bus system memory protection
unit (SMPU) with 16 region descriptors each
– Register protection
• Clock generation
– 40 MHz external crystal (XOSC)
– 16 MHz Internal oscillator (IRCOSC)
– Dual system PLL with one frequency modulated
phase-locked loop (FMPLL)
– Low-jitter PLL
• Functional safety
– Enables ASIL-B applications
– Fault Collection and Control Unit (FCCU) for fault
collection and fault handling
– Memory Error Management Unit (MEMU) for
memory error management
– Safe eDMA controller
– Self-Test Control Unit (STCU2)
– Error Injection Module (EIM)
– On-chip voltage monitoring
– Clock Monitor Unit (CMU)
Document Number S32R372
Rev. 4, 08/2018
S32R372
• Security
– Cryptographic Security Engine (CSE2)
– Supports censorship and life-cycle management
• Timers
– Two Periodic Interval Timers (PIT) with 32-bit
counter resolution
– Two System Timer Module (STM)
– Two Software Watchdog Timers (SWT)
– One eTimer module with 6 channels each
– One FlexPWM module for 12 PWM signals
• Communication interfaces
– Two Serial Peripheral interface (SPI) modules
– One LINFlexD module
– Two inter-IC communication interface (I2C)
modules
– Two FlexCAN modules supporting CAN FD with
configurable buffers
• Debug functionality
– 4-pin JTAG interface and Nexus/Aurora interface
for serial high-speed tracing
– e200z7 core: Nexus development interface (NDI)
per IEEE-ISTO 5001-2012 Class 3+
• Two analog-to-digital converters (SAR ADC)
– Each ADC supports up to 16 input channels
– Cross Trigger Unit (CTU)
• On-chip voltage DC/DC regulator for core supply
generation (VREG)
• Two Temperature Sensors (TSENS)
NXP reserves the right to change the production detail specifications as may be
required to permit improvements in the design of its products.


NXP Semiconductors Electronic Components Datasheet

S32R372 Datasheet

32-bit CPU

No Preview Available !

Table of Contents
1 Introduction........................................................................................ 3
8.3 Flash memory module life specifications................................31
1.1 Chip comparison..................................................................... 3
8.4 Data retention vs program/erase cycles...................................32
1.2 Feature list............................................................................... 4
8.5 Flash memory AC timing specifications.................................32
1.3 Block diagram......................................................................... 8
8.6 Flash memory read wait-state and address-pipeline control
2 Ordering parts.....................................................................................9
settings.....................................................................................33
2.1 Determining valid orderable parts...........................................9
9 Communication modules................................................................... 34
3 Part identification............................................................................... 9
9.1 SPI timing specifications.........................................................34
3.1 Description.............................................................................. 9
9.2 LINFlexD timing specifications..............................................39
3.2 Format..................................................................................... 9
9.3 I2C timing .............................................................................. 39
3.3 Fields....................................................................................... 9
10 Debug modules...................................................................................40
4 General............................................................................................... 11
10.1 JTAG/CJTAG interface timing .............................................. 40
4.1 Introduction............................................................................. 11
10.2 Nexus Aurora debug port timing.............................................43
4.2 Absolute maximum ratings..................................................... 11
11 WKPU/NMI timing specifications.....................................................44
4.3 Operating conditions............................................................... 13
12 External interrupt timing (IRQ pin)................................................... 45
4.4 Supply current characteristics................................................. 14
13 Temperature sensor electrical characteristics.....................................45
4.5 Voltage regulator electrical characteristics............................. 15
14 Radar module..................................................................................... 46
4.6 Electromagnetic Compatibility (EMC) specifications............ 19
14.1 MIPICSI2 D-PHY electrical and timing specifications.......... 46
4.7 Electrostatic discharge (ESD) characteristics......................... 19
14.2 MIPICSI2 disclaimer...............................................................49
5 I/O Parameters....................................................................................20
15 Thermal characteristics...................................................................... 50
5.1 I/O pad DC electrical characteristics ......................................20
15.1 General notes for specifications at maximum junction
5.2 I/O pad AC specifications....................................................... 21
temperature..............................................................................51
5.3 Aurora LVDS driver electrical characteristics........................ 22
15.2 References............................................................................... 53
5.4 Reset pad electrical characteristics..........................................22
16 Packaging........................................................................................... 53
6 Peripheral operating requirements and behaviors.............................. 24
17 Reset sequence................................................................................... 54
6.1 Clocks and PLL Specifications............................................... 24
17.1 Reset sequence duration.......................................................... 54
7 Analog................................................................................................ 27
17.2 Reset sequence description......................................................54
7.1 ADC electrical characteristics.................................................27
18 Power sequencing requirements.........................................................57
8 Memory modules............................................................................... 29
19 Package pinouts and signal descriptions............................................ 58
8.1 Flash memory program and erase specifications.................... 29
20 Release Notes..................................................................................... 59
8.2 Flash memory Array Integrity and Margin Read
specifications........................................................................... 30
S32R372 Data Sheet, Rev. 4, 08/2018
2
NXP Semiconductors


Part Number S32R372
Description 32-bit CPU
Maker NXP
Total Page 3 Pages
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