NT5CC128M8FN sdram equivalent, 1gb sdram.
* JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM
* Data Integrity - A.
The chip is designed to comply with all key DDR3(L) DRAM key features and all of the control and address inputs are syn.
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