NT5CC128M16IP - Industrial and Automotive DDR3(L) 2Gb SDRAM
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Download the NT5CC128M16IP datasheet PDF.
This datasheet also covers the NT5CB256M8IN variant, as both devices belong to the same industrial and automotive ddr3(l) 2gb sdram family and are provided as variant models within a single manufacturer datasheet.
Key Features
JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Power Saving Mode - Partial Array Self Refresh (PASR) 1 - Power Down Mode.
Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (.
Full PDF Text Transcription for NT5CC128M16IP (Reference)
Note: Below is a high-fidelity text extraction (approx. 800 characters) for
NT5CC128M16IP. For precise diagrams, and layout, please refer to the original PDF.
ustrial and Automotive DDR3(L) 2Gb SDRAM Features JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes Power Saving Mode - Partial Array Self Refresh (PASR) 1 - Power Down Mode Signal Integrity - Configurable DS for system compatibility - Configurable On-Die Termination - ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (240 ohm ± 1%) Signal Synchronization - Write Leveling via MR settings 6 - Read Leveling via MPR
NT5CC128M16IP Datasheet
