Download the NT5CC128M8FN datasheet PDF.
This datasheet also covers the NT5CB128M8FN variant, as both devices belong to the same 1gb sdram family and are provided as variant models within a single manufacturer datasheet.
JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM.
Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes.
Power Saving Mode - Partial Array Self Refresh (PASR)1 - Power Down Mode.
Signal Integrity - Configurable DS for system compatibility
- Configurable On-Die Termination
- ZQ Calibration for DS/ODT impedance accuracy via external ZQ pad (2.