NT5CC128M8DN
Description
The 1Gb Double-Data-Rate-3 (DDR3/L) B-die DRAMs is double data rate architecture to achieve high-speed operation. It is internally configured as an eight bank DRAM.
Key Features
- 1.5V ± 0.075V & 1.35V -0.067/+0.1V (JEDEC Standard Power Supply)
- VDD= VDDQ= 1.35V (1.283~1.45V ) Backward compatible to VDD= VDDQ= 1.5V ±0.075V Supports DDR3L devices to be backward compatible in 1.5V applications
- The timing specification of high speed bin is backward compatible with low speed bin
- 8 Internal memory banks (BA0- BA2)
- Differential clock input (CK, )
- Programmable Latency: 5, 6, 7, 8, 9,
