NT5DS128M4BG
Features
CAS Latency and Frequency
CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200
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- DDR 512M bit, die B, based on 110nm design rules
- Double data rate architecture: two data transfers per clock cycle
- Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver
- DQS is edge-aligned with data for reads and is centeraligned with data for writes
Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions mands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2 / 2.5 (6K & 75B), 2.5 / 3 (5T) Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval 2.5V (SSTL_2 patible) I/O VDD = VDDQ =...
