NT5DS16M16BG Datasheet | Nanya Techology

Features CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 - - - - - - - - - - - - - - Double data rate architecture: two data transfers per clock cycle - Bidirectional data strobe (DQS) is transmitted and received with data, to be used in capturing data at the receiver - DQS is edge-aligned with data for reads and is centeraligned with data for writes - Differential clock inputs (CK and CK) Four internal banks for concurrent operation Data mask (DM) for write data DLL aligns DQ and DQS transitions with CK transitions mands entered on each positive CK edge; data and data mask referenced to both edges of DQS Burst lengths: 2, 4, or 8 CAS Latency: 2.5, 3 Auto Precharge option for each burst access Auto Refresh and Self Refresh Modes 7.8µs Maximum Average Periodic Refresh Interval SSTL_2 patible I/O interface VDDQ = 2.6V ± 0.1V VDD = 2.6V ± 0.1V Lead-free and Halogen-free product available Description The 256Mb DDR SDRAM is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM. tion may be enabled to provide a self-timed row precharge that is initiated at the end of the burst access. As with standard SDRAMs, the pipelined, multibank architec The 256Mb DDR SDRAM uses a double-data-rate architecture of DDR SDRAMs allows for concurrent operation, ture to achieve high-speed operation. The double data rate thereby providing high effective bandwidth by hiding row prearchitecture is essentially a 2n prefetch architecture with an charge and activation time. interface designed to transfer two data words per clock cycle . An auto refresh mode is provided along with a power-saving Data Shee at the I/O pins. A single read or write access for the 256Mb Power Down mode. All inputs are patible with the JEDEC DDR SDRAM effectively consists of a single 2n-bit wide, one Standard for SSTL_2. All outputs are SSTL_2, Class II clock cycle data transfer at the internal...