octal d flip-flop.
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Ideal buffer for MOS microprocessor or memory Eight edge-triggered D flip-flops Buffered common clock Buffered asynchronous Master Reset See ’F377 for cl.
where the true output only is required and the Clock and Master Reset are common to all storage elements
Features
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The ’F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously The register is fully edge-triggered The stat.
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