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National Semiconductor Electronic Components Datasheet

74F273 Datasheet

Octal D Flip-Flop

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May 1995
54F 74F273
Octal D Flip-Flop
General Description
The ’F273 has eight edge-triggered D-type flip-flops with in-
dividual D inputs and Q outputs The common buffered
Clock (CP) and Master Reset (MR) inputs load and reset
(clear) all flip-flops simultaneously
The register is fully edge-triggered The state of each D in-
put one setup time before the LOW-to-HIGH clock tran-
sition is transferred to the corresponding flip-flop’s Q out-
put
All outputs will be forced LOW independently of Clock or
Data inputs by a LOW voltage level on the MR input The
device is useful for applications where the true output only is
required and the Clock and Master Reset are common to all
storage elements
Features
Y Ideal buffer for MOS microprocessor or memory
Y Eight edge-triggered D flip-flops
Y Buffered common clock
Y Buffered asynchronous Master Reset
Y See ’F377 for clock enable version
Y See ’F373 for transparent latch version
Y See ’F374 for TRI-STATE version
Y Guaranteed 4000V minimum ESD protection
Commercial
74F273PC
74F273SC (Note 1)
74F273SJ (Note 1)
Military
54F273DM (Note 2)
54F273FM (Note 2)
54F273LM (Note 2)
Package
Number
N20A
J20A
M20B
M20D
W20A
E20A
Package Description
20-Lead (0 300 Wide) Molded Dual-In-Line
20-Lead Ceramic Dual-In-Line
20-Lead (0 300 Wide) Molded Small Outline JEDEC
20-Lead (0 300 Wide) Molded Small Outline EIAJ
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier Type C
Note 1 Devices also available in 13 reel Use suffix e SCX and SJX
Note 2 Military grade device with environmental and burn-in processing Use suffix e DMQB FMQB and LMQB
Logic Symbols
IEEE IEC
TL F 9511 – 3
TRI-STATE is a registered trademark of National Semiconductor Corporation
C1995 National Semiconductor Corporation TL F 9511
TL F 9511 – 5
RRD-B30M75 Printed in U S A


National Semiconductor Electronic Components Datasheet

74F273 Datasheet

Octal D Flip-Flop

No Preview Available !

Connection Diagrams
Pin Assignment for
DIP SOIC and Flatpak
Pin Assignment
for LCC
Unit Loading Fan Out
TL F 9511–1
54F 74F
Pin Names
Description
U L Input IIH IIL
HIGH LOW Output IOH IOL
D0 – D7
MR
CP
Q0 – Q7
Data Inputs
Master Reset (Active LOW)
Clock Pulse Input (Active Rising Edge)
Data Outputs
10 10
10 10
10 10
50 33 3
20 mA b0 6 mA
20 mA b0 6 mA
20 mA b0 6 mA
b1 mA 20 mA
TL F 9511 – 2
Mode Select-Function Table
Operating Mode
Reset (Clear)
Load ‘1’
Load ‘0’
Inputs
MR CP
LX
HL
HL
Dn
X
h
l
Output
Qn
L
H
L
H e HIGH Voltage Level steady state
h e HIGH Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
L e LOW Voltage Level steady state
I e LOW Voltage Level one setup time prior to the LOW-to-HIGH clock
transition
X e Immaterial
L e LOW-to-HIGH clock transition
Logic Diagram
TL F 9511 – 4
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays
2


Part Number 74F273
Description Octal D Flip-Flop
Maker National
Total Page 8 Pages
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