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74F273 - Octal D-Type Flip-Flop

General Description

The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs.

The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously.

The register is fully edge-triggered.

Key Features

  • s Ideal buffer for MOS microprocessor or memory s Eight edge-triggered D-type flip-flops s Buffered common clock s Buffered, asynchronous Master Reset s See 74F377 for clock enable version s See 74F373 for transparent latch version s See 74F374 for 3-STATE version Ordering Code: Order Number 74F273SC 74F273SJ 74F273PC Package Number M20B M20D N20A Package.

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Full PDF Text Transcription (Reference)

The following content is an automatically extracted verbatim text from the original manufacturer datasheet and is provided for reference purposes only.

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74F273 Octal D-Type Flip-Flop April 1988 Revised August 1999 74F273 Octal D-Type Flip-Flop General Description The 74F273 has eight edge-triggered D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip-flops simultaneously. The register is fully edge-triggered. The state of each D input, one setup time before the LOW-to-HIGH clock transition, is transferred to the corresponding flip-flop’s Q output. All outputs will be forced LOW independently of Clock or Data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the Clock and Master Reset are common to all storage elements.