74F273A Datasheet | Philips Semiconductors

FEATURES - High impedance inputs for reduced loading (20µA in Low and High states) - Ideal buffer for MOS microprocessor or memory - Eight edge- triggered D- type flip- flops - Buffered mon clock - Buffered asynchronous Master Reset - See 74F377A for clock enable version - See 74F373 for transparent latch version - See 74F374 for 3- State version DESCRIPTION The 74F273 has eight edge- triggered D- type flip- flops with individual D inputs and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip- flops simultaneously. The register is fully edge- triggered. The state of each D input, one setup time before the Low- to- High clock transition, is transferred to the corresponding flip- flop’s Q output. All outputs will be forced Low independently of Clock or Data inputs by a Low voltage level on the MR input. The device is useful for applications where the true output only is required and the CP and MR are mon to all elements. TYPE 74F273A TYPICAL f MAX 170MHz TYPICAL SUPPLY CURRENT (TOTAL) 25m A ORDERING INFORMATION PACKAGES 20- pin plastic DIP 20- pin plastic SOL MERCIAL RANGE VCC = 5V±10%; Tamb = 0°C to +70°C 74F273AN 74F273AD PKG. DWG. # SOT146-1 SOT163-1 INPUT AND OUTPUT LOADING AND FAN-OUT TABLE PINS D0 - D7 MR CP Q0 - Q7 Data inputs Master Reset input (active- Low) Clock pulse input (active rising edge) Data outputs DESCRIPTION 74F(U.L.) HIGH/LOW 1.0/0.033 1.0/0.033 1.0/0.033 50/33 LOAD VALUE HIGH/LOW 20µA/20µA 20µA/20µA 20µA/20µA 1.0m A/20m A PIN CONFIGURATION MR Q0 D0 D1 Q1 Q2 D2 D3 Q3 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 VCC Q7 D7 D6 Q6 Q5 D5 D4 Q4 CP LOGIC SYMBOL 3 4 7 8 13 14 17 18 D0 11 1 CP MR D1 D2 D3 D4 D5 D6 D7 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 GND 10 2 VCC = Pin 20 GND = Pin...