74F273A Overview
The 74F273 has eight edge triggered D type flip flops with individual D inputs and Q outputs. The mon buffered Clock (CP) and Master Reset (MR) inputs load and reset (clear) all flip flops simultaneously. The register is fully edge triggered.
74F273A Key Features
- High impedance inputs for reduced loading (20µA in Low and High states)
- Ideal buffer for MOS microprocessor or memory
- Eight edge-triggered D-type flip-flops
- Buffered mon clock
- Buffered asynchronous Master Reset
- See 74F377A for clock enable version
- See 74F373 for transparent latch version
- See 74F374 for 3-State version DESCRIPTION
