dual rank 8-bit tri-state shift register.
Y Y Y Y
Y Y Y Y Y
Registers are edge-triggered by the positive transition of the clock All inputs are PNP transistors Input disable dominates over output disable Output.
These circuits are TRI-STATE edge-triggered 8-bit I O registers in parallel with 8-bit serial shift registers which are capable of operating in any of the following modes parallel load from I O pins to register ‘‘A’’ parallel transfer down from regis.
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