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54ABT16374 Datasheet

16-Bit D Flip-Flop with TRI-STATE Outputs

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July 1998
54ABT16374
16-Bit D Flip-Flop with TRI-STATE® Outputs
General Description
The ABT16374 contains sixteen non-inverting D flip-flops
with TRI-STATE outputs and is intended for bus oriented ap-
plications. The device is byte controlled. A buffered clock
(CP) and Output Enable (OE) are common to each byte and
can be shorted together for full 16-bit operation.
Features
n Separate control logic for each byte
n 16-bit version of the ABT374
n Edge-triggered D-type inputs
n Buffered Positive edge-triggered clock
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Guaranteed latch-up protection
n Standard Microcircuit Drawing (SMD) 5962-9320101
Ordering Code:
Commercial
54ABT16374W-QML
Package
Number
WA48A
48-Lead Cerpack
Package Description
Connection Diagram
Logic Symbol
Pin Assignment for Cerpack
Pin Description
DS100224-1
Pin
Names
OEn
CPn
D0– D15
O0– O15
Description
TRI-STATE Output Enable Input (Active Low)
Clock Pulse Input (Active Rising Edge)
Data Inputs
TRI-STATE Outputs
DS100224-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100224
PrintDate=1998/07/14 PrintTime=11:05:34 43604 ds100224 Rev. No. 1 cmserv Proof
www.national.com
1
1


National Semiconductor Electronic Components Datasheet

54ABT16374 Datasheet

16-Bit D Flip-Flop with TRI-STATE Outputs

No Preview Available !

Functional Description
The ABT16374 consists of sixteen edge-triggered flip-flops
with individual D-type inputs and TRI-STATE true outputs.
The device is byte controlled with each byte functioning iden-
tically, but independent of the other. The control pins can be
shorted together to obtain full 16-bit operation. Each byte
has a buffered clock and buffered Output Enable common to
all flip-flops within that byte. The description which follows
applies to each byte. Each flip-flop will store the state of their
individual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CPn) transition. With the
Output Enable (OEn) LOW, the contents of the flip-flops are
available at the outputs. When OEn is HIGH, the outputs go
to the high impedance state. Operation of the OEn input
does not affect the state of the flip-flops.
Logic Diagrams
Truth Tables
Inputs
CP1
N
OE1
L
NL
LL
XH
Inputs
CP2
N
OE2
L
NL
LL
XH
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Byte 1 (0:7)
D0– D7
H
L
X
X
D8– D15
H
L
X
X
Outputs
O0– O7
H
L
(Previous)
Z
Outputs
O8– O15
H
L
(Previous)
Z
Byte 2 (8:15)
DS100224-3
DS100224-4
www.national.com
2
PrintDate=1998/07/14 PrintTime=11:05:34 43604 ds100224 Rev. No. 1 cmserv Proof
2


Part Number 54ABT16374
Description 16-Bit D Flip-Flop with TRI-STATE Outputs
Maker National Semiconductor
Total Page 6 Pages
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