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54ABT16373 Datasheet

16-Bit Transparent Latch with TRI-STATE Outputs

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July 1998
54ABT16373
16-Bit Transparent Latch with TRI-STATE® Outputs
General Description
The ABT16373 contains sixteen non-inverting latches with
TRI-STATE outputs and is intended for bus oriented applica-
tions. The device is byte controlled. The flip-flops appear
transparent to the data when the Latch Enable (LE) is HIGH.
When LE is low, the data that meets the setup time is
latched. Data appears on the bus when the Output Enable
(OE) is LOW. When OE is HIGH, the outputs are in high Z
state.
Features
n Separate control logic for each byte
n 16-bit version of the ABT373
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Guaranteed latch-up protection
n Standard Microcircuit Drawing (SMD) 5962-9320001
Ordering Code:
Military
54ABT16373W-QML
Logic Symbol
Package
Number
WA48A
Package Description
48-Lead Cerpack
Connection Diagram
Pin Assignment for Cerpack
Pin Description
DS100201-1
Pin Names
OEn
LEn
D0– D15
O0– O15
Description
Output Enable Input (Active Low)
Latch Enable Input
Data Inputs
Outputs
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100201
DS100201-2
www.national.com


National Semiconductor Electronic Components Datasheet

54ABT16373 Datasheet

16-Bit Transparent Latch with TRI-STATE Outputs

No Preview Available !

Functional Description
The ABT16373 contains sixteen D-type latches with
TRI-STATE standard outputs. The device is byte controlled
with each byte functioning identically, but independent of the
other. Control pins can be shorted together to obtain full
16-bit operation. The following description applies to each
byte. When the Latch Enable (LEn) input is HIGH, data on
the Dn enters the latches. In this condition the latches are
transparent, i.e., a latch output will change states each time
its D input changes. When LEn is LOW, the latches store in-
formation that was present on the D inputs a setup time pre-
ceding the HIGH-to-LOW transition of LEn. The TRI-STATE
standard outputs are controlled by the Output Enable (OEn)
input. When OEn is LOW, the standard outputs are in the
2-state mode. When OEn is HIGH, the standard outputs are
in the high impedance mode but this does not interfere with
entering new data into the latches.
Logic Diagrams
Truth Tables
Inputs
LE1
OE1
D0– D7
XH
X
HL
L
HL
H
LL
X
Outputs
O0– O7
Z
L
H
(Previous)
Inputs
Outputs
LE2
X
OE2
H
D8– D15
X
O8– O15
Z
HL
L
L
HL
H
H
LL
X (Previous)
H = High Voltage Level
L = Low Voltage Level
X = Immaterial
Z = High Impedance
Previous = previous output prior to HIGH to LOW transition of LE
DS100201-3
www.national.com
DS100201-4
2


Part Number 54ABT16373
Description 16-Bit Transparent Latch with TRI-STATE Outputs
Maker National Semiconductor
Total Page 6 Pages
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