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National Semiconductor Electronic Components Datasheet

54ABT374 Datasheet

Octal D-Type Flip-Flop

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July 1998
54ABT374
Octal D-Type Flip-Flop with TRI-STATE® Outputs
General Description
The ’ABT374 is an octal D-type flip-flop featuring separate
D-type inputs for each flip-flop and TRI-STATE outputs for
bus-oriented applications. A buffered Clock (CP) and Output
Enable (OE) are common to all flip-flops.
Features
n Edge-triggered D-type inputs
n Buffered positive edge-triggered clock
n TRI-STATE outputs for bus-oriented applications
n Output sink capability of 48 mA, source capability of
24 mA
n Guaranteed multiple output switching specifications
n Output switching specified for both 50 pF and 250 pF
loads
n Guaranteed simultaneous switching, noise level and
dynamic threshold performance
n Guaranteed latchup protection
n High impedance glitch free bus loading during entire
power up and power down cycle
n Non-destructive hot insertion capability
n Standard Microcircuit Drawing (SMD) 5962-9314901
Ordering Code
Military
54ABT374J/883
54ABT374W/883
54ABT374E/883
Package
Number
J20A
W20A
E20A
Connection Diagrams
Pin Assignment for DIP
and Flatpak
Package Description
20-Lead Ceramic Dual-In-Line
20-Lead Cerpack
20-Lead Ceramic Leadless Chip Carrier, Type C
Pin Assignment
for LCC
DS100207-1
DS100207-2
TRI-STATE® is a registered trademark of National Semiconductor Corporation.
© 1998 National Semiconductor Corporation DS100207
www.national.com


National Semiconductor Electronic Components Datasheet

54ABT374 Datasheet

Octal D-Type Flip-Flop

No Preview Available !

Pin Descriptions
Pin
Names
D0– D7
CP
OE
O0– O7
Description
Data Inputs
Clock Pulse Input (Active
Rising Edge)
TRI-STATE Output Enable
Input (Active LOW)
TRI-STATE Outputs
Functional Description
The ’ABT374 consists of eight edge-triggered flip-flops with
individual D-type inputs and TRI-STATE true outputs. The
buffered clock and buffered Output Enable are common to all
flip-flops. The eight flip-flops will store the state of their indi-
vidual D inputs that meet the setup and hold time require-
ments on the LOW-to-HIGH Clock (CP) transition. With the
Output Enable (OE) LOW, the contents of the eight flip-flops
are available at the outputs. When OE is HIGH, the outputs
are in a high impedance state. Operation of the OE input
does not affect the state of the flip-flops.
Function Table
Inputs
Internal
OE CP D
Q
H HL
NC
H HH
H NL
NC
L
H NH
L NL
H
L
L NH
H
L HL
NC
L HH
NC
H = HIGH Voltage Level
L = LOW Voltage Level
X = Immaterial
Z = High Impedance
N = LOW-to-HIGH Transition
NC = No Change
Outputs
O
Z
Z
Z
Z
L
H
NC
NC
Function
Hold
Hold
Load
Load
Data Available
Data Available
No Change in Data
No Change in Data
Logic Diagram
DS100207-3
Please note that this diagram is provided only for the understanding of logic operations and should not be used to estimate propagation delays.
www.national.com
2


Part Number 54ABT374
Description Octal D-Type Flip-Flop
Maker National Semiconductor
Total Page 12 Pages
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