74LS76 Datasheet | onsemi

SN74LS76A Dual JK Flip-Flop with Set and Clear The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIGH, the inputs are enabled and data will be accepted. The Logic Level of the J and K inputs will perform according to the Truth Table as long as minimum set-up times are observed. Input data is transferred to the outputs on the HIGH-to-LOW clock transitions. http://onsemi. LOW POWER SCHOTTKY MODE SELECT - TRUTH TABLE OPERATING MODE Set Reset (Clear) - Undetermined Toggle Load “0” (Reset) Load “1” (Set) Hold - INPUTS SD L H L H H H H CD H L L H H H H J X X X h l h l K X X X h h l l OUTPUTS Q H L H q L H q Q L H H q H L q 16 1 Both outputs will be HIGH while both SD and CD are LOW, but the output states are unpredictable if SD and CD go HIGH simultaneously. PLASTIC N SUFFIX CASE 648 H, h = HIGH Voltage Level L, I = LOW Voltage Level X = Immaterial l, h (q) = Lower case letters indicate the state of the referenced input i, h (q) = (or output) one setup time prior to the HIGH- to- LOW clock transition 16 1 SOIC D SUFFIX CASE 751B GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current - High Output Current - Low Min 4.75 0 Typ 5.0 25 Max 5.25 70 - 0.4 8.0 Unit V °C m A m A ORDERING INFORMATION Device SN74LS76AN SN74LS76AD Package 16 Pin DIP 16 Pin Shipping 2000 Units/Box 2500/Tape & Reel © Semiconductor ponents Industries, LLC, 1999 December, 1999 - Rev. 6 Publication Order Number: SN74LS76A/D SN74LS76A LOGIC DIAGRAM 2 Q Q 16 1 4 CLEAR (CD) J SET (SD) K K CP J C Q D 3 VCC = PIN 5 GND = PIN 13 CLOCK (CP) 14 SD Q 15 12 6 9 K CP J C Q D 8 10 LOGIC SYMBOL 7 SD Q 11 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Limits Symbol VIH VIL VIK VOH Parameter Input HIGH Voltage Input LOW Voltage Input Clamp Diode Voltage Output HIGH Voltage 2.7 - 0.65 3.5 0.25 VOL O...