74LS76 Datasheet and Specifications PDF

SN74LS76A Dual JK Flip-Flop with Set and Clear The SN74LS76A offers individual J, K, Clock Pulse, Direct Set and Direct Clear inputs. These dual flip-flops are designed so that when the clock goes HIG.

e the state of the referenced input i, h (q) = (or output) one setup time prior to the HIGH
*to
*LOW clock transition 16 1 SOIC D SUFFIX CASE 751B GUARANTEED OPERATING RANGES Symbol VCC TA IOH IOL Parameter Supply Voltage Operating Ambient Temperature Range Output Current
* High Output Current
* Low.

19.20 20.00 Max 16 9 7.40 Max 6.30 Unit: mm 1 1.3 1.11 Max 8 0.51 Min 2.54 Min 5.06 Max 7.62 2.54 ± 0.25 0.48 ± 0.10 0.25 – 0.05 0° – 15° Hitachi Code JEDEC EIAJ Weight (reference value) + 0.

s or any third party’s patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party’s rights, including intellectual property rights, in connection with use of the informat.

SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121 – DECEMBER 1983 – REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conf.

UAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121
* DECEMBER 1983
* REVISED MARCH 1988
*POST OFFICE BOX 655303 DALLAS, TEXAS 75265 5 SN5476, SN54LS76A SN7476, SN74LS76A DUAL J-K FLIP-FLOPS WITH PRESET AND CLEAR SDLS121
* DECEMBER 1983
* REVISED MARCH 1988
*6 POST OFFICE BOX 655303 DALLAS, TEXAS 75.

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